1. Field of the Invention
The present invention relates to a solid-state imaging device, which uses the MOS image sensor of a threshold voltage modulation type used for a video camera, an electronic camera, an image input camera, a scanner, a facsimile or the like.
2. Description of the Related Art
As mass productivity is high for a semiconductor image sensor, e.g., a CCD image sensor, a MOS image sensor, and so on, the semiconductor image sensor has been used for almost all imaging devices with the progress made in a fine pattern technology.
In recent years, particularly the MOS image sensor has been reevaluated because it is advantageous in that power consumption is small compared with the CCD image sensor, and a sensor device and a peripheral circuit device can be manufactured by the same CMOS technology.
In line with such a tendency, the inventors made improvements on the MOS image sensor, and filed the application for a patent regarding a sensor device having a carrier pocket (heavily doped buried layer) 25 below the channel region of an insulated gate field effect transistor for light signal detection (hereinbelow, referred to as PXMOSFET) (Japanese Patent Application Hei 10 (1998)-186453). A patent therefor has been granted (registered No. 2935492).
The described MOS image sensor has a structure shown in FIGS. 1 and 2: FIG. 1 being a plan view; and FIG. 2 being a sectional view taken on line Ixe2x80x94I of FIG. 1. In this structure as shown in FIGS. 1 and 2, a unit pixel 101 is composed of a photo-diode 111, and a PXMOSFET 112 adjacent to the photo-diode 111. The MOS image sensor is constructed by arraying such pixels 101 in a matrix form. The photo-diode 111 and the PXMOSFET 112 are communicated by p-type well regions 15a and 15b. In the PXMOSFET 112, a gate electrode 19 has a ring shape, an n-type source region 16 is formed in the center thereof, and an n-type drain region 17a is formed to surround the outer periphery of the gate electrode 19. A p-type hole pocket 25 is formed to surround the source region 16 in the well region 15b near the source region, below the gate electrode 19.
Adjacent pixels 101 are isolated from each other by a pixel isolation region. The pixel isolation region is composed of an insulating isolation region 14 formed in a substrate surface by a local oxidation of silicon (LOCOS) method, and a p-type diffusing isolation region 13 formed in a semiconductor substrate provided below the insulating isolation region 14.
During initialization period in the MOS image sensor, a high positive voltage is applied to each electrode to be depleted to sweep photo-generated holes remaining in the hole pocket 25 to the substrate. During storing period, the photo-diode 111 is irradiated with a light collected by a microlens to generate photo-generated holes, and then the holes are moved to be stored in the hole pocket 25. Then, during reading period, a light signal is detected by detecting the threshold voltage of the PXMOSFET 112 modulated in proportion to the stored amount of photo-generated holes.
In the solid-state imaging device, the pixel isolation region formed by the LOCOS method is not suited for microfabrication of pixel 101 with respect to the structure. Thus, a further improvement may be required in order to meet a request for the microfabrication possibly made with a higher definition of an image in the future.
When a pixel pitch is reduced to achieve a higher density of a pixel array, since the structure of the peripheral part of the gate electrode 19 is complex compared with the photo-diode 111, a reduction rate of the gate electrode 19 is limited compared with that of the photo-diode 111. Consequently, at present or in the near future, an area of the gate electrode 19 may become to account for more than seventy percent to a total area of a pixel.
In the case of reducing a pixel pitch while maintaining an area of a light-detecting portion as wider as possible under such circumstances, the light-detecting portion of the photo-diode 111 is to be formed in a thin and long rectangular shape. Thus, if a light collection method by the microlens is applied, there may be caused a situation that an optical spot diameter is out of the light-detecting portion in the short side direction of the same finally as microfabrication is further advanced. In such a case, the quantity of incident light becomes short in both ends of the short side direction. Consequently, an output from the image sensor provably decreases and outputs between pixels provably results in a lack of uniformity even when a uniform pattern is photographed.
In addition, in the imaging device using the CCD device, resolution is improved by employing the three-plate system in which three CCD elements are arranged corresponding to primary colors separated by a prism. On the other hand, in the MOS image sensor, there has been expected an improvement of resolution by a single-plate system in which a light signal including primary colors is obtained with one imaging device element using a color filter. That leads to a good use of the features of the MOS image sensor, i.e., low power consumption, and a compact size.
The present invention provides a solid-state imaging device having a structure suited for microfabrication of a pixel, and capable of miniaturizing the imaging device as a whole.
It is an object of the present invention to provide a solid-state imaging device capable of improving resolution by a single-plate system.
Moreover, it is an object of the present invention to provide a solid-state imaging device having more effective pixel arrangement in preventing a decrease of output and a lack of uniformity of outputs among pixels.
The formation of an insulating film by a local oxidation of silicon (LOCOS) method is disadvantageous for microfabrication because the region for forming an isolation insulating film is expanded by an amount of more than a mask size due to the formation of bird""s beak.
According to the present invention, as shown in FIGS. 3, 4A, 4C, 5, and 6, a pixel isolation region for isolating adjacent pixels 101 from each other is provided with a diffusing isolation region 53 having same conductivity as a drain region 57a. The diffusing isolation region 53 is formed deeper than the well regions 54a and 54b to contact the regions 52a and 52b under the well regions 54a and 54b while the diffusing isolation region 53 contact the impurity region 57 and the drain region 57a above the well regions 54a and 54b. Therefore, the well regions 54a and 54b are surrounded in the entire periphery thereof by the impurity region 57, the drain region 57a, the regions 52a and 52b and the diffusing isolation region 53. And during operating such imaging device, the photo-generated charges in the well regions 54a and 54b cannot move out of the well regions 54a and 54b due to a potential generated in the pn junction. In such manner, adjacent pixels can be separated from each other by the diffusing isolation region 53.
In other words, since the pixel isolation is carried out only by the diffusing isolation region 53 without using any isolation insulating films by the LOCOS method, no bird""s beak is formed to prevent the pixel isolation region from being expanded by an amount more than the mask size. Thus, the pixel 101 can be microfabricated, and thus the imaging device is miniaturized as a whole.
In the solid-state imaging device of the present invention, pixels 101, each thereof having a PXMOSFET 112, are arrayed in a matrix form, a plurality of gate electrodes 59 of PXMOSFETs 112 are disposed at at least four directions among the peripheral part of a photodiode 111, and a plurality of photo-diodes 111 are disposed at at least four directions among the peripheral part of the gate electrode of the PXMOSFET 112. In this case, one pixel 101 is provided with the ring-shaped gate electrode 59, in which a planar shape of the outer peripheral part thereof is formed to be polygonal having four or more sides, alternately circular. One pixel 101 is provided as well with the photo-diode 111 which is formed adjacently to at least one side of the polygonal shape or a part of the circumference of the circular shape of the gate electrode 59.
FIG. 7 is an example of above arrangement. The components inside the pixel 101 may be arranged such that a direction from the gate electrode 59 to the photo-diode 111 can coincide with an oblique direction with respect to a row and a column directions, and the pixels may be arrayed in a matrix form. FIGS. 11, 12, 14 and 15 are examples of such arrangement. In other words, the photo-diode 111 is disposed among so-called lattices composed of row-directed lines of the gate electrode 59 and column-directed lines of the same. Accordingly, it is possible to facilitate the formation of a photo-diode 111 provided with a light-detecting portion having so-called isotropic expansion, i.e., in which a ratio of short and long sides of a light-detecting portion having, e.g., a square shape, approaches 1 while the forming area of the gate electrode 59 is secured.
In FIG. 8, the light-detection portions are arranged with a pitch Pr on the same column-directed line, and the light-detection portions are arranged with a pitch Pc on the same row-directed line. A shift of 1/2Pc occurs between the adjacent row-directed lines, and a shift of 1/2Pr occurs between the adjacent column-directed lines.
This arrangement corresponds to FIGS. 17, 18, 19 and 20. In FIGS. 18, 19 and 20, the components inside the pixel 101 are arranged such that a direction from the gate electrode 59 to the photo-diode 111 can coincide with a parallel direction with respect to the row or column direction, and adjacent pixels are arranged such that the directions from the gate electrode 59 to the photo-diode 111 turn to the same directions. In FIG. 17, adjacent pixels are arranged such that the directions from the gate electrode 59 to the photo-diode 111 turn to the opposite directions.
In other words, the gate electrode 59 and the photo-diodes 111 are arranged alternately on the row-directed line and the column-directed line. Accordingly, a row pitch and a column pitch can be scaled down while securing a forming area of the photo-diode 111 provided with a light-detecting portion having so-called isotropic expansion and a sufficient forming area of the gate electrode 59.
In the case of FIG. 21 where pixels are arranged without any contrivance, an irradiation optical spot is moved out of the light-detecting portion to cause a reduction in the output of an optical electric signal from the pixel. On the other hand, in the above pixel arrangement of the present invention, since the photo-diode 111 provided with a light detecting portion having more isotropic expansion is obtained, an irradiation optical spot is set in the light detecting portion as shown in FIGS. 22A and 22B. Thus, it is possible to prevent a reduction in the output of an optical electric signal from the pixel and a lack of uniformity of outputs among pixels, which are caused by the case where the irradiation optical spot can no longer be fit on the light-detecting portion.
In addition, in the planar arrangement of the pixels 101 in the solid-state imaging device, as shown in FIGS. 17 to 20, the gate electrodes 59 with respect to the photo-diodes 111 belonging to adjacent row-directed lines are sequentially connected to form the one row. The arrangement of the photo-diodes 111 in the one row shapes in a zigzag manner along the row direction. This zigzag arrangement results in a same advantage as so-called pixel shifting in the solid-state imaging device of the three-plate system using a CCD device. In other words, a pitch between adjacent row lines substantially becomes narrower than the row pitch Pr compared with no pixel shifting, so that a light signal irradiated between the rows with pitch Pr is captured as well. Accordingly, resolution can be enhanced in the single-plate system.
The pixel arrangements as shown in FIG. 9 and FIG. 10 as well are in a scope of the present invention. Both arrangements are similar to FIG. 8. In FIG. 9, the pitch of the photo-diodes 111 on the row-directed line is wider than that in the regular arrangement. In FIG. 10, the pitch of the photo-diodes 111 on the column-directed line is wider than that in the regular arrangement. Accordingly, since the forming area of the gate electrode can be taken wider, these arrangements are advantageous for case that there is a need for an increase of an amount of photo-generated carriers stored in the heavily doped buried layer while the row pitch or the column pitch is scaled down.